#ifndef __APP_ARM_H_
#define __APP_ARM_H_

#include "stdint.h"
//#include "S32K144.h"
//+add 2022/1/22 cv28
//PTE10
//#define	EN_VCC_3V3_INDEX        			PCC_PORTE_INDEX
#define	EN_VCC_3V3_PIN_NIM     				(10)
#define EN_VCC_3V3_PIN_DISABLE             	PORTE->PCR[EN_VCC_3V3_PIN_NIM] = PORT_PCR_MUX(0)
#define	EN_VCC_3V3_PIN_MODE(MUX,HL) 		(PORTE->PCR[EN_VCC_3V3_PIN_NIM] &= (~PORT_PCR_MUX_MASK),\
											 PORTE->PCR[EN_VCC_3V3_PIN_NIM] |= PORT_PCR_MUX(MUX),\
											 PTE->PDDR  &=  ~(1<<EN_VCC_3V3_PIN_NIM), \
											 PTE->PDDR  |=  (HL<<EN_VCC_3V3_PIN_NIM))
#define EN_VCC_3V3_ON()						(PTE->PDOR |= (1<<EN_VCC_3V3_PIN_NIM))
#define EN_VCC_3V3_OFF()					(PTE->PDOR &= ~(1<<EN_VCC_3V3_PIN_NIM))	


//#define	CV_PWR_PSEQ1_INDEX        		PCC_PORTE_INDEX
#define	CV_PWR_PSEQ1_PIN_NIM     			(3)
#define CV_PWR_PSEQ1_PIN_DISABLE	        PORTE->PCR[CV_PWR_PSEQ1_PIN_NIM] = PORT_PCR_MUX(0)
#define	CV_PWR_PSEQ1_PIN_MODE(MUX,HL)    	(PORTE->PCR[CV_PWR_PSEQ1_PIN_NIM] &= (~PORT_PCR_MUX_MASK),\
											PORTE->PCR[CV_PWR_PSEQ1_PIN_NIM] |= PORT_PCR_MUX(MUX),\
											PTE->PDDR  &=  ~(1<<CV_PWR_PSEQ1_PIN_NIM), \
											PTE->PDDR  |=  (HL<<CV_PWR_PSEQ1_PIN_NIM))
#define CV_PWR_PSEQ1_ON()					(PTE->PDOR |= (1<<CV_PWR_PSEQ1_PIN_NIM))
#define CV_PWR_PSEQ1_OFF()					(PTE->PDOR &= ~(1<<CV_PWR_PSEQ1_PIN_NIM))

//#define	CV_PWR_PSEQ2_INDEX        		PCC_PORTE_INDEX
#define	CV_PWR_PSEQ2_PIN_NIM     			(4)
#define CV_PWR_PSEQ2_PIN_DISABLE	        PORTE->PCR[CV_PWR_PSEQ2_PIN_NIM] = PORT_PCR_MUX(0)
#define	CV_PWR_PSEQ2_PIN_MODE(MUX,HL)    	(PORTE->PCR[CV_PWR_PSEQ2_PIN_NIM] &= (~PORT_PCR_MUX_MASK),\
											PORTE->PCR[CV_PWR_PSEQ2_PIN_NIM] |= PORT_PCR_MUX(MUX),\
											PTE->PDDR  &=  ~(1<<CV_PWR_PSEQ2_PIN_NIM), \
											PTE->PDDR  |=  (HL<<CV_PWR_PSEQ2_PIN_NIM))
#define CV_PWR_PSEQ2_ON()					(PTE->PDOR |= (1<<CV_PWR_PSEQ2_PIN_NIM))
#define CV_PWR_PSEQ2_OFF()					(PTE->PDOR &= ~(1<<CV_PWR_PSEQ2_PIN_NIM))

//#define	EN_P5V_INDEX        			PCC_PORTD_INDEX
#define	EN_P5V_PIN_NIM     					(6)
#define EN_P5V_PIN_DISABLE              	PORTD->PCR[EN_P5V_PIN_NIM] = PORT_PCR_MUX(0)
#define	EN_P5V_PIN_MODE(MUX,HL)   			(PORTD->PCR[EN_P5V_PIN_NIM] &= (~PORT_PCR_MUX_MASK),\
											PORTD->PCR[EN_P5V_PIN_NIM] |= PORT_PCR_MUX(MUX),\
											PTD->PDDR  &=  ~(1<<EN_P5V_PIN_NIM), \
											PTD->PDDR  |=  (HL<<EN_P5V_PIN_NIM))
#define EN_P5V_ON()							(PTD->PDOR |= (1<<EN_P5V_PIN_NIM))
#define EN_P5V_OFF()						(PTD->PDOR &= ~(1<<EN_P5V_PIN_NIM))


//#define	CV_PWR_PSEQ3_INDEX        		PCC_PORTE_INDEX
#define	CV_PWR_PSEQ3_PIN_NIM     			(5)
#define CV_PWR_PSEQ3_PIN_DISABLE           	PORTE->PCR[CV_PWR_PSEQ3_PIN_NIM] = PORT_PCR_MUX(0)
#define	CV_PWR_PSEQ3_MODE(MUX,HL)     		(PORTE->PCR[CV_PWR_PSEQ3_PIN_NIM] &= (~PORT_PCR_MUX_MASK),\
											PORTE->PCR[CV_PWR_PSEQ3_PIN_NIM] |= PORT_PCR_MUX(MUX),\
											PTE->PDDR  &=  ~(1<<CV_PWR_PSEQ3_PIN_NIM), \
											PTE->PDDR  |=  (HL<<CV_PWR_PSEQ3_PIN_NIM))
#define CV_PWR_PSEQ3_ON()					(PTE->PDOR |= (1<<CV_PWR_PSEQ3_PIN_NIM))
#define CV_PWR_PSEQ3_OFF()					(PTE->PDOR &= ~(1<<CV_PWR_PSEQ3_PIN_NIM))

//#define	PWR_CV_3V0_INDEX        		PCC_PORTE_INDEX
#define	PWR_CV_3V0_PIN_NIM     				(7)
#define PWR_CV_3V0_PIN_DISABLE              PORTE->PCR[PWR_CV_3V0_PIN_NIM] = PORT_PCR_MUX(0)
#define	PWR_CV_3V0_PIN_MODE(MUX,HL)     	(PORTE->PCR[PWR_CV_3V0_PIN_NIM] &= (~PORT_PCR_MUX_MASK),\
											PORTE->PCR[PWR_CV_3V0_PIN_NIM] |= PORT_PCR_MUX(MUX),\
											PTE->PDDR  &=  ~(1<<PWR_CV_3V0_PIN_NIM), \
											PTE->PDDR  |=  (HL<<PWR_CV_3V0_PIN_NIM))
#define PWR_CV_3V0_ON()						(PTE->PDOR |= (1<<PWR_CV_3V0_PIN_NIM))
#define PWR_CV_3V0_OFF()					(PTE->PDOR &= ~(1<<PWR_CV_3V0_PIN_NIM))								

//#define	MCU_RESET_SOC_INDEX        		PCC_PORTD_INDEX
#define	MCU_RESET_SOC_PIN_NIM     			(5)
#define MCU_RESET_SOC_PIN_DISABLE           	PORTD->PCR[MCU_RESET_SOC_PIN_NIM] = PORT_PCR_MUX(0)
#define	MCU_RESET_SOC_PIN_MODE(MUX,HL)  	(PORTD->PCR[MCU_RESET_SOC_PIN_NIM] &= (~PORT_PCR_MUX_MASK),\
											PORTD->PCR[MCU_RESET_SOC_PIN_NIM] |= PORT_PCR_MUX(MUX),\
											PTD->PDDR  &=  ~(1<<MCU_RESET_SOC_PIN_NIM), \
											PTD->PDDR  |=  (HL<<MCU_RESET_SOC_PIN_NIM))
#define MCU_RESET_SOC_ON()					(PTD->PDOR |= (1<<MCU_RESET_SOC_PIN_NIM))
#define MCU_RESET_SOC_OFF()					(PTD->PDOR &= ~(1<<MCU_RESET_SOC_PIN_NIM))

#define	DET_PGOOD_PIN_INDEX        				PCC_PORTC_INDEX
#define	DET_PGOOD_PIN_NIM     				(5)
#define DET_PG00D_PIN_DISABLE             	PORTC->PCR[DET_PGOOD_PIN_NIM] = PORT_PCR_MUX(0)
#define	DET_PGOOD_PIN_MODE(MUX,HL) 			(PORTC->PCR[DET_PGOOD_PIN_NIM] &= (~PORT_PCR_MUX_MASK),\
											PORTC->PCR[DET_PGOOD_PIN_NIM] |= PORT_PCR_MUX(MUX),\
											PTC->PDDR  &=  ~(1<<DET_PGOOD_PIN_NIM), \
											PTC->PDDR  |=  (HL<<DET_PGOOD_PIN_NIM))	
#define DET_PGOOD_READ_STATUS				((PTC->PDIR & (1<<DET_PGOOD_PIN_NIM))==0)


extern void RequestSocUpgrade(void);
extern void TranferSocUdsData(uint8_t *writeBuffer, uint32_t writeLength, uint16_t sequenceNumber);
extern void InformSocUpgradeOver(void);
extern void TranferSocSignatureDataFrame(uint8_t type, uint8_t *buffer, uint8_t len, uint8_t index);
#endif